A High Speed Matrix Multiplication Base Algorithm Implementation for Improved Computational Time and Throughput
Research Area: | Volume 3 Issue 2, March. 2014 | Year: | 2014 |
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Type of Publication: | Article | Keywords: | HDL Synthesis, RTL, FIFO, Structural Style of Modelling, BlockRAM |
Authors: |
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Journal: | IJEIR | Volume: | 3 |
Number: | 2 | Pages: | 195-197 |
Month: | March | ||
Abstract: | Matrix multiplication is used in applications such as signal and image processing, graphics and robotics etc. In this work we design and discuss the results of implementing matrix-vector multiplication which is computationally very exhaustive. It requires several multiply and add units. Processing system take numerous clock cycles to perform all the necessary multiply add operations. The overall performance is restricted by the number of multiplications and additions that could be done in parallel. Matrix multiplication architecture is based on serial-parallel sign multiplier and adder component. Our proposed design provides better speed, better throughput structural design for matrix multiplier as compared to antecedent reportable implementation of matrix operation with cut back gate count mistreatment VHDL. |
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Full text: IJEIR_887_Final.pdf
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