Area Optimized Adder Design Using Carry Selection Logic in Power-Constrained Environments

Research Area: Volume 6,Issue 1, Jan. 2017 Year: 2017
Type of Publication: Article Keywords: Area, Speed, power, Transmission Gate, Carry Select
  • Abhishek Chourasia
  • Prof. Umashankar Kurmi
Journal: IJEIR Volume: 6
Number: 1 Pages: 48-50
Month: January
ISSN: 2277-5668
The major drawback of the parallel adder is its slow speed due to the time it takes to propagate the carry. Also in parallel adder the delay increases linearly with the bit length. To overcome this limitation some papers work on carry look ahead adder but on the area draw back. But CLA requires large number of transistor for design with increase area. The main purpose of this paper is to design the speed limiting and area efficient adder design with optimize power. For speed limitation the carry select technique if use and for optimized power and reduced area. The design logic has been design using 50nm technology on Micro wind layout simulator. Compared to a conventional adder with this architecture, The layout design by dynamic CMOS logic optimizes the area in term of number of transistors with the comparison of conventional adder logic

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